SEVEN SEGMENT

On the FPGA board, we can find 4 displays of seven-segment. We can light four of them simultaneously. We need a counter that is used to light the 4 displays of seven-segment one by one. But because the counter is relatively fast, we won't be able to see the actual shifting process of the seven-segment displays. It would look like four of the seven-segment displays light up simultaneously. The input of the code would be in form of 8-bit unsigned. Then it would be processed through and display the number based on the input given. The number that can be displayed is 0,1,2,3,4,5,6,7,8,9, it can also display a couple of alphabets but that depends on the truth table of the corresponding 7 segments.

We recommend to code with ISE Design Suite 14.7 as it can also be used to test the code in VHDL. However, to upload the code into BASYS 3, you will need to install Vivado (ver. 2015.4 or 2016.4) and write the constraint file with .xdc extension.

INPUT

clock_100Mhz : in STD_LOGIC; (For timing purposes)

reset : in STD_LOGIC; (For resetting the code)

input_value : in STD_LOGIC_VECTOR ( 15 downto 0 ); (Input from the substractor )

INTERNAL SIGNAL

signal displayed_number: STD_LOGIC_VECTOR (15 downto 0); (for counting decimal number to be displayed on 4-digit 7-segment display)

signal LED_BCD: STD_LOGIC_VECTOR (3 downto 0); (For seven-segment activation)

signal refresh_counter: STD_LOGIC_VECTOR (19 downto 0); (for creating 10.5ms refresh period)

signal LED_activating_counter: std_logic_vector(1 downto 0); ( for creating 4 LED-activating signals)

OUTPUT Anode_Activate: out STD_LOGIC_VECTOR (3 downto 0); ( To activate either one of the four seven-segment display)

LED_out: out STD_LOGIC_VECTOR (6 downto 0)); ( To activate a certain number of LED located in each seven-segment displays)

Click HERE for the code sample

The input of the code would be 16-bit unsigned which then be processed through the code. From here, the 16-bit number then is divided into four 4-bit unsigned which are then each sent to the seven-segment display for display. The value of the 4-bit unsigned will be matched according to the truth table of the seven-segment. Then the matching one will cause the output of the matching BCD to be displayed on the seven-segment. In order to display all the 16-bit integers, 4 seven-segment display is needed but it is impossible to activate all of them in one time. This is why we need a counter to run all four seven-segment alternatively according to the clock inserted into the counter. Since the clock supposed to be moving at an incredible frequency, for us, we won't be able to catch the switching process of a seven-segment to another one.